Electronic circuit for providing a desired common mode voltage to a differential output of an amplifier stage

ABSTRACT

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     An electronic circuit for supplying a common mode voltage to a differential output of an amplifier stage (AMPSTG). The common mode voltage at the terminals (1) and (2) is approximately equal to the reference voltage (V CM ). Transistors (T 1 -T 4 ) are biased in their linear region whereas transistors (T 5  - T 8 ) are biased in their saturation region. In order to choose the lowest possible reference voltage (VCM), the dimensioning of the transistors (T 1 -T 4 ) is such that the currents through the transistors (T 1 -T 3 ) have equal current densities, and the current through the transistor (T 4 ) has a current density which is a factor N smaller than the former current densities. The factor N is determined by the ratio of the nominal value of the current through the transistor (T 1 ) and the minimum value of the current through the transistor (T 1 ).

[0001] The invention relates to an electronic circuit for providing a desired common mode voltage to a differential output of an amplifier stage, which differential output comprises a first output terminal and a second output terminal, comprising a supply terminal; a first field effect transistor with a source coupled to the supply terminal; a second field effect transistor with a source coupled to the supply terminal; a third field effect transistor with a source coupled to the supply terminal and with a gate coupled so as to receive a reference voltage; a first cascode circuit with a first main current electrode coupled to a drain of the first field effect transistor, with a second main current electrode coupled to a gate of the first field effect transistor and to the first output terminal, and with a control electrode; a second cascode circuit with a first main current electrode coupled to a drain of the second field effect transistor and to the drain of the first field effect transistor, with a second main current electrode coupled to a gate of the second field effect transistor and to the second output terminal, and with a control electrode coupled to the control electrode of the first cascode circuit; a third cascode circuit with a first main current electrode coupled to a drain of the third field effect transistor, with a second main current electrode coupled to the control electrode of the first cascode circuit, and with a control electrode coupled to the control electrode of the first cascode circuit; and current means for providing a current through the third field effect transistor and the third cascode circuit.

[0002] Such an electronic circuit is known from the prior art. The known electronic circuit is shown in FIG. 1 and comprises: first to third field effect transistors (T₁ to T₃), fifth to seventh cascode field effect transistors (T₅ to T₇), and a current source I for supplying a current through the third and the seventh field effect transistor T₃ and T₇. The electronic circuit receives a supply voltage between a first supply terminal V_(ss) and a second supply terminal V_(DD.)

[0003]FIG. 1 also shows a model of a differential output of an amplifier stage AMPSTG, which differential output comprises a first output terminal 1 and a second output terminal 2. The sources of the first to third transistors T₁, to T₃ are connected to the first supply terminal V_(ss). The drains of the first and second transistors T₁, and T₂ and the sources of the fifth and sixth transistors T₅ and T₆ are interconnected. The gate of the first transistor T₁ and the drain of the fifth transistor T₅ are connected to the first output terminal 1. The gate of the second transistor T₂ and the drain of the sixth transistor T₆ are connected to the second output terminal 2. The gates of the fifth, sixth, and seventh transistors T₅ to T₇ and the drain of the seventh transistor T₇ are interconnected. The drain of the third transistor T₃ is connected to the source of the seventh transistor T₇. The gate of the third transistor T₃ receives a reference voltage V_(CM). The voltages at the output terminals 1 and 2 are referenced V_(Out1) and V_(Out2) , respectively. The common mode voltage at the output terminals 1 and 2 per definition then is equal to the sum of V_(Out1) and V_(OUT2) divided by 2. The electronic circuit is dimensioned such that the common mode voltage is equal to the reference voltage V_(CM). This is represented in equation 1 $\begin{matrix} {\frac{V_{out1} + V_{out2}}{2} = V_{CM}} & (1) \end{matrix}$

[0004] It should be noted that the first and the second transistor must always be set for their linear operation ranges if the electronic circuit is to operate correctly. In the known electronic circuit, the reference voltage V_(CM), and accordingly also the common mode voltage at the first and the second output terminal 1 and 2, is usually chosen to be approximately equal to half the supply voltage. The reference voltage V_(CM) is often greater than necessary then, but a sufficient margin is present for accommodating, for example, spreads in transistor parameters.

[0005] It is a disadvantage of the known electronic circuit, accordingly, that it is less suitable for applications in which an operation at a minimum supply voltage is desired.

[0006] It is an object of the invention to provide an electronic circuit capable of supplying a lowest possible common mode voltage to a differential output of an amplifier stage.

[0007] According to the invention, the electronic circuit mentioned in the opening paragraph is for this purpose characterized in that the electronic circuit further comprises: a fourth field effect transistor with a source coupled to the first supply terminal; a fourth cascode circuit with a first main current electrode coupled to a drain of the fourth field effect transistor, with a second main current electrode coupled to a gate of the fourth field effect transistor, and with a control electrode coupled to the control electrode of the first cascode circuit; further current means for supplying a current through the fourth field effect transistor and the fourth cascode circuit; and voltage-generating means coupled in series between the further current means and the second main current electrode of the fourth cascode circuit, and in that the gate of the third field effect transistor is coupled to the voltage-generating means for receiving the reference voltage, and in that the first, the second, and the third field effect transistor are dimensioned such that they have approximately the same current densities, and in that the fourth field effect transistor is dimensioned such that it has a current density which is a factor N smaller than said current densities, said factor N being approximately equal to the ratio of the nominal current to the minimum current through the first field effect transistor.

[0008] It is achieved thereby that the reference voltage to be defined is substantially independent of transistor parameters.

[0009] An embodiment of an electronic circuit according to the invention is characterized in that the first cascode circuit comprises a fifth transistor with a first and a second main current electrode which form the first and the second main current electrode, respectively, of the first cascode circuit, and with a control electrode which forms the control electrode of the first cascode circuit; and in that the second cascode circuit comprises a sixth transistor with a first and a second main current electrode which form the first and the second main current electrode, respectively, of the second cascode circuit, and with a control electrode which forms the control electrode of the second cascode circuit; and in that the third cascode circuit comprises a seventh transistor with a first and a second main current electrode which form the first and the second main current electrode, respectively, of the third cascode circuit, and with a control electrode which forms the control electrode of the third cascode circuit; and in that the fourth cascode circuit comprises an eighth transistor with a first and a second main electrode which form the first and the second main current electrode, respectively, of the fourth cascode circuit, and with a control electrode which forms the control electrode of the fourth cascode circuit.

[0010] A very simple embodiment for the cascode circuits is obtained thereby. The fifth to seventh transistors are either all implemented with bipolar transistors of the same conductivity type or all implemented with field effect transistors of the same conductivity type.

[0011] An embodiment of an electronic circuit according to the invention is furthermore characterized in that the fifth, the sixth, the seventh, and the eighth transistor are dimensioned such that they have approximately the same current densities.

[0012] As a result, the potentials at the drains of the first to fourth field effect transistors are approximately equal. This achieves a better accuracy for defining the common mode voltage at the first and the second output terminal 1 and 2.

[0013] Further advantageous embodiments of the electronic circuit according to the invention are defined in claims 4 to 8. It should be noted in this connection that the presence of the limiting means prevents the first or second field effect transistor from being fully switched off in the case of a too high differential output voltage at the differential output of the amplifier stage. A full switch-off of the first or second field effect transistor may lead to an unacceptably long recovery time in the known electronic circuit.

[0014] The invention will now be explained in more detail with reference to the accompanying drawing, in which:

[0015]FIG. 1 shows a known electronic circuit which supplies a common mode voltage to a differential output of an amplifier stage,

[0016]FIG. 2 is a circuit diagram of a first embodiment of an electronic circuit according to the invention, and

[0017]FIG. 3 is a circuit diagram of a second embodiment of an electronic circuit according to the invention.

[0018] The same components or elements have been given the same reference symbols in these Figures.

[0019]FIG. 2 is a circuit diagram of a first embodiment of an electronic circuit according to the invention. The circuit comprises the same elements as those shown in the circuit of FIG. 1, supplemented with the following elements:

[0020] a fourth field effect transistor,

[0021] an eighth cascode transistor,

[0022] voltage-generating means VGMNS which in this case are constructed with a resistor R, and

[0023] further current means I_(F) for supplying a current through the fourth field effect transistor T₄ and the eighth cascode transistor T8.

[0024] The further current source I_(F) is coupled on the one hand to the second supply terminal V_(DD) and on the other hand via the resistor R to the drain of the eighth cascode transistor T₈ and the gate of the fourth field effect transistor T₄. The gate of the third field effect transistor T₃ is coupled to the common junction point of the further current source I_(F) and the resistor R. The source of the fourth field effect transistor T₄ is coupled to the first supply terminal V_(ss). The drain of the fourth field effect transistor T₄ is coupled to the source of the eighth cascode transistor T_(8.) The gate of the eighth cascode transistor T₈ is coupled to the gate of the seventh cascode transistor T₇. Alternative electronic circuits could be used instead of the cascode transistors T₅ to T_(8.) This is diagrammatically indicated in FIG. 2 with the reference symbols CSC₁ to CSC₄. The currents through the transistors T₁, T₂, T₅, and T₆ are supplied from the output terminals 1 and 2 of the amplifier stage AMPSTG. The respective currents supplied by the current source I and the further current source I_(F) may be chosen to be the same. This, however, is not necessary. What is the point in dimensioning of the circuit is that the current densities of the currents through the transistors T₁, T₂, and T₃ are approximately the same, and that the current density of the current through the fourth transistor T₄ is a factor N lower than the current densities mentioned above of the first to third transistors T₁ to T_(3.)

[0025] The current densities of the currents through the fifth to eighth transistors T₅ to T₈ are approximately equal. The dimensioning is such, furthermore, that the first and the second transistor T₁ and T₂ always operate in their linear regions.

[0026] The nominal current through the first transistor T₁ is the current which flows through the first transistor T₁ when the potentials V_(Out1) and V_(Out2) are equal to one another. This is the case when there is no signal at the differential output of the amplifier stage AMPSTG. If there is a signal at the differential output of the amplifier stage AMPSTG, the potentials V_(Out1) and V_(Out2) will be different. The current flowing through the first transistor T₁ will be a minimum when the potential V_(OUT1) is a minimum, and accordingly the potential of V_(Out2) is a maximum. The electronic circuit is dimensioned such that the ratio of the nominal current to the minimum current through the first transistor T₁ is approximately equal to said factor N.

[0027] Apart from the equation 1 given above, the electronic circuit also complies with the mathematical relations as given by equations 2 to 6 below.

V_(out1)−V_(th)>V_(ds1,2)   (2)

V_(out2)−V_(th)>V_(ds1,2)  (3)

V_(out,min)=V_(th)+V_(ds1,2)   (4)

V_(out,max)=2.V_(CM)−V_(out,min)=2.V_(CM) −V_(th) −V_(ds1,2)  (5)

[0028] $\begin{matrix} {\beta_{1,2} > {2 \cdot \frac{\left( {N - 1} \right)^{2}}{N} \cdot \frac{I}{\left( {V_{{out},\max} - V_{{out},\min}} \right)^{2}}}} & (6) \end{matrix}$

[0029] V_(th) is the threshold voltage of a field effect transistor. V_(ds1,2) is the voltage between the drain and the source of the transistors T₁ and T₂. V_(out,min) is the minimum voltage of V_(OUT1) or V_(OUT2). V_(out,max) is the maximum voltage of V_(out1) or V_(out2). β_(1,2) is the gain factor of the transistors T₁ and T₂. I is the nominal current through the first transistor T_(1.)

[0030] Since the voltage between the gate and the source of the first transistor T₁ is equal to V_(out1), and the voltage between the gate and the source of the second transistor T₂ is equal to V_(out2) it follows from equations 2 and 3 that the first and the second transistor T₁ and T₂ are always set for their linear operation regions. A suitable choice for the reference voltage V_(CM) and a suitable choice of V_(dS1,2) render it possible to calculate the values for V_(out,min) and V_(out,max) by means of the equations 4 and 5. Furthermore, the minimum gain factor β_(1,2) can be calculated from equation 6. The factor N is chosen such that the ratio of the nominal current to the minimum current through the first transistor T₁ is equal to this factor N. To ensure that the first and the second transistor are always set for their linear operation regions, it is advisable to choose a value for the current gain β_(1.2) which is slightly greater than the minimum value following from equation 6, for example greater by a factor 2.

[0031]FIG. 3 is a circuit diagram of a second embodiment of an electronic circuit according to the invention. A difference with the circuit diagram of FIG. 2 is that the voltage-generating means VGMNS are constructed in a different manner, i.e. by means of a diode D which is coupled in the forward direction between the further current source I_(F) and the drain of the eighth transistor T₈. The diode D may be provided, for example, with a field effect transistor connected as a diode. A voltage divider is connected in parallel to the diode D, which divider comprises a series arrangement of a first resistor R₁ and a second resistor R₂. The central tap of this voltage divider is coupled to the gate of the third transistor T₃. Another difference is that the circuit diagram of FIG. 3 includes limiting means VLMT which are coupled between the first terminal 1 and the second terminal 2. The limiting means VLMT are constructed with a first limiting diode D₁ and a second limiting diode D₂ here, by way of example. The first limiting diode D₁ and the second limiting diode D₂ may each be fitted, for example, with a field effect transistor connected as a diode. The first limiting diode D₁ and the second limiting diode D₂ are connected in anti-parallel. The limiting means VLMT limit the maximum voltage difference between the first terminal 1 and the second terminal 2. It is ensured thereby that the first and the second transistor T₁ and T₂ can never be fully switched off, which would have the result that the electronic circuit would need a long recovery time. The diodes D, and D₁ and D₂ may possibly be mutually matched.

[0032] Although the electronic circuit may be used to advantage in an integrated circuit, it may alternatively be composed from discrete components. It is also possible to replace all p-conductivity type transistors with n-conductivity type transistors, provided all n-conductivity type transistors are replaced with p-conductivity type transistors at the same time. the first (T₁), the second (T₂), and the third (t₃) field effect transistor are dimensioned such that they have approximately the same current densities, and in that the fourth field effect transistor (T₄) is dimensioned such that it has a current density which is a factor N smaller than said current densities, said factor N being approximately equal to the ratio of the nominal current to the minimum current through the first field effect transistor (T₁). ? 

2. An electronic circuit as claimed in claim 1, characterized in that the first cascode circuit (CSC1) comprises a fifth transistor (T5) with a first and a second main current electrode which form the first and the second main current electrode, respectively, of the first cascode circuit (CSC1), and with a control electrode which forms the control electrode of the first cascode circuit (CSC1); and in that the second cascode circuit (CSC2) comprises a sixth transistor (T6) with a first and a second main current electrode which form the first and the second main current electrode, respectively, of the second cascode circuit (CSC2), and with a control electrode which forms the control electrode of the second cascode circuit (CSC2); and in that the third cascode circuit (CSC3) comprises a seventh transistor (T7) with a first and a second main current electrode which form the first and the second main current electrode, respectively, of the third cascode circuit (CSC3), and with a control electrode which forms the control electrode of the third cascode circuit (CSC3); and in that the fourth cascode circuit (CSC4) comprises an eighth transistor (T8) with a first and a second main electrode which form the first and the second main current electrode, respectively, of the fourth cascode circuit (CSC4), and with a control electrode which forms the control electrode of the fourth cascode circuit (CSC4).
 3. An electronic circuit as claimed in claim 2 , characterized in that the fifth (T₅), the sixth (T₆), the seventh (T₇), and the eighth (T₈) transistor are dimensioned such that they have approximately the same current densities.
 4. An electronic circuit as claimed in claim 1 , 2 , or 3, characterized in that the voltage-generating means (VGMNS) comprise a resistive element (R) which is connected in series between the further current means (I_(F)) and the second main current electrode of the fourth cascode circuit (CSC₄).
 5. An electronic circuit as claimed in claim 1 , 2 , or 3, characterized in that the voltage-generating means (VGMNS) comprise: a diode (D) which is coupled in forward the first (T₁), the second (T₂), and the third (T₃) field effect transistor are dimensioned such that they have approximately the same current densities, and in that the fourth field effect transistor (T₄) is dimensioned such that it has a current density which is a factor N smaller than said current densities, said factor N being approximately equal to the ratio of the nominal current to the minimum current through the first field effect transistor (T₁).
 6. An electronic circuit as claimed in claim 1 , 2 , 3, 4, or 5, characterized in that the electronic circuit further comprises limiting means (VLMT) for limiting the maximum voltage difference between the first termninal (1) and the second terminal (2).
 7. An electronic circuit as claimed in claim 6 , characterized in that the limiting means (VLMT) comprise: a first limiting diode (D₁); and a second limiting diode (D2), and in that the first limiting diode (D₁) and the second limiting diode (D₂) are connected in anti-parallel.
 8. An electronic circuit as claimed in claim 7, characterized in that the absolute value of the maximum voltage difference between the first terminal (1) and the second terminal (2) is approximately equal to the absolute value of the voltage across the diode (D). 